Conventionally, in a semiconductor device equipped with a semiconductor integrated circuit, a technology disclosed in Patent Document 1 is known, for example, as a technology for decreasing power supply impedance with respect to the semiconductor integrated circuit. According to the technology disclosed in Patent Document 1, the antiresonance impedance of power supply impedance is decreased by configuring a series resonance circuit from a pattern unit including three conductor patterns between a power supply terminal and a ground terminal of a semiconductor element (semiconductor integrated circuit).
Patent Document 1: Japanese Patent Application Laid-Open No. 2014-175628